View AS1374-BWLT1833_7519558.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

austriamicrosystems ag is now ams ag the technical content of this austriamicrosystems datasheet is still valid. contact information: headquarters: ams ag tobelbaderstrasse 30 8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 e - mail: ams_sales @ams.com please visit our website at www.ams.com
as1374 dual 200ma, low-noise, high-psr r, low dropout regulators datasheet www.austriamicrosystems.com/ldos/as1374 revision 1.8 1 - 18 1 general description the as1374 is a low-noise, low-dropout linear regulator with two separated outputs. designed to deliver 200ma continuous output current at each output pin, the ldos can achieve a low 120mv dropout for 200ma load current and are designed and optimized to work with low-cost, small-capacitance ceramic capacitors. an integrated p-channel mosfet pass transistor allows the devices to maintain extremely low quiescent current (30a). the as1374 uses an advanced architecture to achieve ultra-low output voltage noise of 20v rms and a power-supply rejection-ratio of better than 85db (@ 1khz). two active-high enable pins allows to switch on or off each output independently from each other. the as1374 requires only 1f output capacitor for stability at any load. the device is available in a 6-bump wlp package. figure 1. as1374 - typical application circuit 2 key features ?? preset output voltages: 1.2v to 3.6v (in 50mv steps) ?? output noise: 20v rms @ 100hz to 100khz ?? power-supply rejection ratio: 85db @ 1khz ?? low dropout: 120mv @ 200ma load ?? stable with 1f ceramic capacitor for any load ?? guaranteed 200ma output ?? pull-down option in shutdown (factory set) ?? extremely-low quiescent current: 30a ?? excellent load/line transient ?? overcurrent and thermal protection ?? 6-bump wlp package 3 applications the devices are ideal for mobile phones, wireless phones, pdas, handheld computers, mobile phone base stations, bluetooth portable radios and accessories, wireless lans, digital cameras, personal audio devices, and any other portable, battery-powered application. as1374 5 gnd 4 en 2 2 vdd 3 out 1 6 en 1 c1 1f input 2v to 5.5v output1 1.2v to 3.6v 1 out 2 c2 1f c3 1f output2 1.2v to 3.6v ams ag technical content still valid
as1374 datasheet - pin assignments www.austriamicrosystems.com/ldos/as1374 revision 1.8 2 - 18 4 pin assignments figure 2. pin assignments (top view) 4.1 pin descriptions table 1. pin descriptions pin number pin name description 1out 2 regulated output voltage 2. bypass this pin with a capacitor to gnd. see application information for capacitor selection. 2vdd input supply 3out 1 regulated output voltage 1. bypass this pin with a capacitor to gnd. see application information for capacitor selection. 4en 2 enable 2. pull this pin to logic low to disable regulated output 2 voltage. 5gnd ground 6en 1 enable 1. pull this pin to logic low to disable regulated output 1 voltage. as1374 4 13 6 5 2 ams ag technical content still valid
as1374 datasheet - absolute maximum ratings www.austriamicrosystems.com/ldos/as1374 revision 1.8 3 - 18 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 4 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments electrical parameters vdd to gnd -0.3 7 v all other pins to gnd -0.3 v dd + 0.3 v output short-circuit duration infinite input current (latch-up immunity) -100 100 ma norm: jedec 78 electrostatic discharge electrostatic discharge hbm 2 kv norm: mil 883 e method 3015 temperature ranges and storage conditions thermal resistance ? ja 201.7 oc/w junction-to-ambient thermal resistance is very dependent on application and board-layout. in situations where high maximum power dissipation exists, special attention must be paid to thermal dissipation during board design. junction temperature +125 oc storage temperature range -55 +150 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. humidity non-condensing 5 85 % ams ag technical content still valid
as1374 datasheet - electrical characteristics www.austriamicrosystems.com/ldos/as1374 revision 1.8 4 - 18 6 electrical characteristics v in = v out + 0.5v, v out = 2.85v, c in = c out = 1f, typical values are at t amb = +25oc (unless otherwise specified). all limits are guaranteed. the parameters with min and max values are guaranteed with production tests or sqc (statistical quality control) me thods . table 3. electrical characteristics symbol parameter condition min typ max unit t amb operating temperature range -40 +85 c v in input voltage range 2 5.5 v ? v out output voltage accuracy i out = 1ma, t amb = +25oc -1 +1 % i out = 100a to 200ma, t amb = +25oc -1.5 +1.5 i out = 100a to 200ma -2.5 +2.5 i out maximum output current each channel 200 ma i gnd ground current one channel on, i out = 50a 25 50 a one channel on, i out = 200ma 30 55 a i limit current limit out = short 210 300 400 ma dropout voltage 1 1. dropout is defined as v in - v out when v out is 100mv below the value of v out for v in = v out + 0.5v. 2v ?? v out ? 2.5v, i out = 100ma 80 150 mv i q quiescent current both channels on, i out = 0.05ma 30 90 a both channels on, v in = v outnom - 0.1v, i out = 0ma 50 v lnr line regulation v in = (v out +0.5v) to 5.5v, i out = 1ma 0.02 %/v v ldr load regulation i out = 1 to 200ma 0.0005 %/ma i shdn shutdown current out 1 and out 2 disable 0.01 2 a psrr ripple rejection f = 1khz, i out = 10ma 85 db f = 10khz, i out = 10ma 65 f = 100khz, i out = 10ma 50 output noise voltage (rms) f = 100hz to 100khz, i load = 20ma 20 v enable enable input bias current 0.01 a enable exit delay 2 2. time needed for v out to reach 90% of final value. both channels initially off 150 s one channel initially off 200 enable logic low level 0.4 v enable logic high level 1.4 v thermal protection t shdn thermal shutdown temperature 160 oc ? t shdn thermal shutdown hysteresis 15 oc c out output capacitor load capacitor range 0.47 10 f maximum esr load 500 m ? ams ag technical content still valid
as1374 datasheet - typical operating characteristics www.austriamicrosystems.com/ldos/as1374 revision 1.8 5 - 18 7 typical operating characteristics v in = v out + 0.5v, v out = 2.85v, c in = c out = 1f, t amb = 25c (unless otherwise specified). figure 3. output voltage vs. temperature figure 4. output voltage vs. input voltage 2.82 2.83 2.84 2.85 2.86 2.87 2.88 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) output voltage (v) ch1 ch2 2.82 2.83 2.84 2.85 2.86 2.87 2.88 3.35 3.85 4.35 4.85 5.35 input voltage (v) output voltage (v) iload = 1ma iload = 10 ma iload = 100ma iload = 200ma figure 5. output voltage vs. load current figure 6. output voltage vs. input voltage - dropout 2.8 2.81 2.82 2.83 2.84 2.85 2.86 2.87 2.88 0 25 50 75 100 125 150 175 200 load current (ma) output voltage (v) -40c +2 5c +8 5c 2.72 2.74 2.76 2.78 2.8 2.82 2.84 2.86 2.75 2.8 2.85 2.9 2.95 3 3.05 input voltage (v) output voltage (v) iload = 100ma iload = 200ma figure 7. dropout voltage vs. load current figure 8. psrr vs. frequency 0 25 50 75 100 125 150 25 50 75 100 125 150 175 200 load current (ma) dropout voltage (v) -40c +2 5c +8 5c 20 30 40 50 60 70 80 90 100 100 1000 10000 100000 frequency (hz) psrr (db) ams ag technical content still valid
as1374 datasheet - typical operating characteristics www.austriamicrosystems.com/ldos/as1374 revision 1.8 6 - 18 figure 9. ground pin current vs. load current figure 10. ground pin current vs. temperature 23 24 25 26 27 28 29 30 31 32 33 0 25 50 75 100 125 150 175 200 load current (ma) ground pin current (a) -40c +2 5c +8 5c 25 26 27 28 29 30 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) ground pin current (a) figure 11. ground pin current vs. input voltage; one channel on, no load figure 12. ground pin current vs. input voltage; one channel on, i load = 200ma 0 10 20 30 40 50 60 012345 input voltage (v) ground pin current (a) -40c +2 5c +8 5c 0 10 20 30 40 50 60 3.35 3.85 4.35 4.85 5.35 input voltage (v) ground pin current (a) -40c +2 5c +8 5c figure 13. ground pin current vs. input voltage; both channels on, no load figure 14. ground pin current vs. input voltage; both channels on, i load = 200ma 0 10 20 30 40 50 60 70 80 90 100 012345 input voltage (v) ground pin current (a) -40c +2 5c +8 5c 0 10 20 30 40 50 60 70 80 90 100 3.35 3.85 4.35 4.85 5.35 input voltage (v) ground pin current (a) -40c +2 5c +8 5c ams ag technical content still valid
as1374 datasheet - typical operating characteristics www.austriamicrosystems.com/ldos/as1374 revision 1.8 7 - 18 figure 15. shutdown current vs. input voltage figure 16. load regulation vs. temperature 0 10 20 30 40 50 60 0.511.522.533.544.555.5 input voltage (v) shutdown current (na) -40c +2 5c +8 5c -0.0012 -0.001 -0.0008 -0.0006 -0.0004 -0.0002 0 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) load regulation (% / ma) ch1 ch2 figure 17. line regulation vs. load current figure 18. line regulation vs. temperature -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 25 50 75 100 125 150 175 200 load current (ma) line regulation (% / v) -40c +2 5c +8 5c -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) line regulation (% / v) iload = 1ma iload = 10 ma iload = 100ma iload = 200ma figure 19. load transient response, crosstalk, between ch1 and ch2, i out = 200ma figure 20. load transient response near dropout, i out = 200ma 20s/div v out2 10mv/div 10mv/div 100ma/div v out1 i out1 20s/div 20mv/div 100ma/div v out1 i out1 ams ag technical content still valid
as1374 datasheet - typical operating characteristics www.austriamicrosystems.com/ldos/as1374 revision 1.8 8 - 18 figure 21. line transient response figure 22. shutdown 100s/div 10mv/div 500mv/div v out1 v in 100s/div v out1 1v/div 2v/div 50ma/div en1 i out1 figure 23. startup of ch1 when ch2 is off figure 24. startup of ch1 when ch2 is on 20s/div v out1 1v/div 2v/div 100ma/div en1 i in 20s/div v out1 1v/div 2v/div 100ma/div en1 i in ams ag technical content still valid
as1374 datasheet - detailed description www.austriamicrosystems.com/ldos/as1374 revision 1.8 9 - 18 8 detailed description figure 25 shows the block diagram of the as1374. it identifies the basics of a series linear regulator employing a p-channel mosfet as t he control element. a stable voltage reference (ref in figure 25 ) is compared with an attenuated sample of the output voltage. any difference between the two voltages (reference and sample) creates an output from the error amplifier that drives the series control eleme nt to reduce the difference to a minimum. the error amplifier incorporates additional buffering to drive the relatively large gate capacitance o f the series pass p- channel mosfet, when additional drive current is required under transient conditions. input supply variations are absorbed by t he series element, and output voltage variations with loading are absorbed by the low output impedance of the regulator. 8.1 output voltage the as1374 deliver preset output voltages from 1.2v to 3.6v, in 50mv increments (see ordering information on page 17) . 8.2 enable the as1374 feature an active high enable mode to shutdown each output independently. driving en 1 low disables output 1, drivin g en 2 low disables output 2. the disabled output enters a high-impedance state. figure 25. as1374 block diagram 8.3 current limit the as1374 include a current limiting circuitry to monitor and control the p-channel mosfet pass transistor?s gate voltage, thu s limiting the device output current to 300ma. note: see table 3 on page 4 for the recommended min and max current limits. the output can be shorted to ground indefinitely without causing damage to the device. 8.4 thermal protection integrated thermal protection circuitry limits total power dissipation in the as1374. when the junction temperature (t j ) exceeds +160oc, the thermal sensor signals the shutdown logic, turning off the p-chann el mosfet pass transistor and allowing the device to cool dow n. the thermal sensor turns the pass transistor on again after the device?s junction temperature drops by 15oc, resulting in a pulsed output d uring continuous thermal-overload conditions. note: thermal protection is designed to protect the devices in the event of fault conditions. for continuous operation, do not exceed the absolute maximum junction temperature rating of +150oc. trimmable reference bandgap + - + - enable logic ch1 thermal protection common logic enable logic ch2 en1 vin en2 o u t 1 g n d o u t 2 as1374 o v e r c u r r e n t p r o t e c t i o n c h 1 o v e r c u r r e n t p r o t e c t i o n c h 2 ams ag technical content still valid
as1374 datasheet - application information www.austriamicrosystems.com/ldos/as1374 revision 1.8 10 - 18 9 application information 9.1 dropout voltage dropout is the input to output voltage difference, below which the linear regulator ceases to regulate. at this point, the outp ut voltage change follows the input voltage change. dropout voltage may be measured at different load currents, but is usually specified at maxim um output. as a result, the mosfet maximum series resistance over temperature is obtained. more generally: v dropout = i load x r series (eq 1) dropout is probably the most important specification when the regulator is used in a battery application. the dropout performan ce of the regulator defines the useful ?end of life? of the battery before replacement or re-charge is required. figure 26. graphical representation of dropout voltage figure 26 shows the variation of v out as v in is varied for a certain load current. the practical value of dropout is the differential voltage (v out - v in ) measured at the point where the ldo output voltage has fallen by 100mv below the nominal, fully regulated output value. the n ominal regulated output voltage of the ldo is that obtained when there is 500mv (or greater) input-output voltage differential. 9.2 efficiency low quiescent current and low input-output voltage differential are important in battery applications amongst others, as the re gulator efficiency is directly related to quiescent current and dropout voltage. efficiency is given by: efficiency = % (eq 2) where: iq = quiescent current of ldo dropout voltage 100mv v in v out v out v in v out v in =v out(typ) +0.5v v in v load i load ? v in i q i load + ?? ----------------------------------------- 100 ? ams ag technical content still valid
as1374 datasheet - application information www.austriamicrosystems.com/ldos/as1374 revision 1.8 11 - 18 9.3 power dissipation maximum power dissipation (pd) of the ldo is the sum of the power dissipated by the internal series mosfet and the quiescent cu rrent required to bias the internal voltage reference and the internal error amplifier, and is calculated as: watts (eq 3) internal power dissipation as a result of the bias current for the internal voltage reference and the error amplifier is calcul ated as: watts (eq 4) total ldo power dissipation is calculated as: watts (eq 5) 9.4 junction temperature under all operating conditions, the maximum junction temperature should not be allowed to exceed 125c (unless otherwise specif ied in the datasheet). limiting the maximum junction temperature requires knowledge of the heat path from junction to case ( ? jc c/w fixed by the ic manufacturer), and adjustment of the case to ambient heat path ( ? ca c/w) by manipulation of the pcb copper area adjacent to the ic position. figure 27. package physical arrangements pd max ?? seriespass ?? i load max ?? = v in max ?? v out min ?? ? ?? pd max ?? bias ?? v in max ?? i q = pd max ?? total ?? pd max ?? seriespass ?? pd max ?? + bias ?? = chip pcb package transfer layer cs-wlp package solder balls ams ag technical content still valid
as1374 datasheet - application information www.austriamicrosystems.com/ldos/as1374 revision 1.8 12 - 18 figure 28. steady state heat flow equivalent circuit total thermal path resistance: r ? ja = r ? jc + r ? cs + r ? sa (eq 6) junction temperature (t j oc) is determined by: t j = (pd (max) x r ? ja ) + t amb oc (eq 7) 9.5 explanation of st eady state specifications 9.5.1 line regulation line regulation is defined as the change in output voltage when the input (or line) voltage is changed by a known quantity. it is a measure of the regulator?s ability to maintain a constant output voltage when the input voltage changes. line regulation is a measure of the d c open loop gain of the error amplifier. more generally: line regulation = and is a pure number (eq 8) in practise, line regulation is referred to the regulator output voltage in terms of % / v out . this is particularly useful when the same regulator is available with numerous output voltage trim options. line regulation = % / v (eq 9) 9.5.2 load regulation load regulation is defined as the change of the output voltage when the load current is changed by a known quantity. it is a measure of the regulator?s ability to maintain a constant output voltage when the load changes. load regulation is a measure of the dc closed loop output resistance of the regulator. more generally: load regulation = and is units of ohms ( ? )(eq 10) in practise, load regulation is referred to the regulator output voltage in terms of % / ma. this is particularly useful when t he same regulator is available with numerous output voltage trim options. load regulation = % / ma (eq 11) junction t j c package t c c pcb/heatsink t s c ambient t a c chip power r ? jc r ? cs r ? sa ? ? ? ? ? ? ? ? ? ? ams ag technical content still valid
as1374 datasheet - application information www.austriamicrosystems.com/ldos/as1374 revision 1.8 13 - 18 9.5.3 setting accuracy accuracy of the final output voltage is determined by the accuracy of the ratio of r1 and r2, the reference accuracy and the in put offset voltage of the error amplifier. when the regulator is supplied pre-trimmed, the output voltage accuracy is fully defined in the output voltage specification. when the regulator has a set terminal, the output voltage may be adjusted externally. in this ca se, the tolerance of the external resistor network must be incorporated into the final accuracy calculation. generally: (eq 12) the reference tolerance is given both at 25c and over the full operating temperature range. 9.5.4 total accuracy away from dropout, total steady state accuracy is the sum of setting accuracy, load regulation and line regulation. generally: total % accuracy = setting % accuracy + load regulation % + line regulation % (eq 13) 9.6 explanation of dynamic specifications 9.6.1 power supply rejection ratio (psrr) known also as ripple rejection, this specification measures the ability of the regulator to reject noise and ripple beyond dc. psrr is a summation of the individual rejections of the error amplifier, reference and ac leakage through the series pass transistor. the specification, in the form of a typical attenuation plot with respect to frequency, shows up the gain bandwidth compromises forced upon the desig ner in low quiescent current conditions. generally: psrr = db using lower case to indicate ac values (eq 14) power supply rejection ratio is fixed by the internal design of the regulator. additional rejection must be provided externally . the as1374 is designed to deliver low noise and high psrr, with low quiescent currents in battery-powered systems. the power-supply rejection is 85db at 1khz and 50db at 100khz. when operating from sources other than batteries, improved supply-noise rejection and transient response are achieved by increasing the values of the input and output capacitors. additional passive lc filtering at the input can provide enhanced rejection at high frequencies. 9.6.2 output capacitor esr the series regulator is a negative feedback amplifier, and as such is conditionally stable. the esr of the output capacitor is usually used to cancel one of the open loop poles of the error amplifier in order to produce a single pole response. excessive esr values may a ctually cause instability by excessive changes to the closed loop unity gain frequency crossover point. the range of esr values for stability is usually shown either by a plot of stable esr versus load current, or a maximum value in the datasheet. some ceramic capacitors exhibit large capacitance and esr variations with variations in temperature. z5u and y5v capacitors may be required to ensure stability at temperatures below t amb = -10c. with x7r or x5r capacitors, a 1f capacitor should be sufficient at all operating temperatures. larger output capacitor values (10f) help to reduce noise and improve load transient-response, stability and power-supply reje ction. 9.6.3 input capacitor an input capacitor at v in is required for stability. it is recommended that a 1.0f capacitor be connected between the as1369 power supply input pin v in and ground (capacitance value may be increased without limit subject to esr limits). this capacitor must be located at a dista nce of not more than 1cm from the v in pin and returned to a clean analog ground. any good quality ceramic, tantalum, or film capacitor may be used at the input. 9.6.4 noise the regulator output is a dc voltage with noise superimposed on the output. the noise comes from three sources; the reference, the error amplifier input stage, and the output voltage setting resistors. noise is a random fluctuation and if not minimized in some app lications, will produce system problems. v out v set ? v set ? ?? r 1 ? r 1 ? r 2 ? r 2 ? ?? ?? log ? v out ? v in ---------------- - ? ams ag technical content still valid
as1374 datasheet www.austriamicrosystems.com/ldos/as1374 revision 1.8 14 - 18 9.6.5 transient response the series regulator is a negative feedback system, and therefore any change at the output will take a finite time to be correc ted by the error loop. this ?propagation time? is related to the bandwidth of the error loop. the initial response to an output transient comes from the output capacitance, and during this time, esr is the dominant mechanism causing voltage transients at the output. more generally: units are volts, amps, ohms. (eq 15) thus an initial +50ma change of output current will produce a -12mv transient when the esr=240m ? . do remember to keep the esr within stability recommendations when reducing esr by adding multiple parallel output capacitors. after the initial esr transient, there follows a voltage droop during the time that the ldo feedback loop takes to respond to t he output change. this drift is approx. linear in time and sums with the esr contribution to make a total transient variation at the output of: units are volts, seconds, farads, ohms. (eq 16) where: c load is output capacitor t= propagation delay of the ldo this shows why it is convenient to increase the output capacitor value for a better support for fast load changes. of course th e formula holds for t < ?propagation time?, so that a faster ldo needs a smaller cap at the load to achieve a similar transient response. for insta nce 50ma load current step produces 50mv output drop if the ldo response is 1sec and the load cap is 1f. there is also a steady state error caused by the finite output impedance of the regulator. this is derived from the load regula tion specification discussed above. 9.6.6 turn on time this specification defines the time taken for the ldo to awake from shutdown. the time is measured from the release of the enable pin to the time that the output voltage is within 5% of the final value. it assumes that the voltage at v in is stable and within the regulator min and max limits. shutdown reduces the quiescent current to very low, mostly leakage values (<1a). 9.6.7 thermal protection to prevent operation under extreme fault conditions, such as a permanent short circuit at the output, thermal protection is bui lt into the device. die temperature is measured, and when a 160c threshold is reached, the device enters shutdown. when the die cools sufficiently , the device will restart (assuming input voltage exists and the device is enabled). hysteresis of 15c prevents low frequency oscillation b etween start-up and shutdown around the temperature threshold. ? v transient ? i output r esr ? ? v transient ? i output r esr t c load ---------------- - + ?? ?? ? ams ag technical content still valid
as1374 datasheet - package drawings and markings www.austriamicrosystems.com/ldos/as1374 revision 1.8 15 - 18 10 package drawin gs and markings the as1374 is available in a 6-bump wlp package. figure 29. 6-bump wlp package notes: 1. ccc ? coplanarity 2. all dimensions are in m. top through view bottom view (ball side) assh xxxx ams ag technical content still valid
as1374 datasheet - package drawings and markings www.austriamicrosystems.com/ldos/as1374 revision 1.8 16 - 18 revision history note: typos may not be explicitly mentioned under revision history. revision date owner description initial revisions 1.7 11 oct, 2011 afe changes made across the document 1.8 12 dec, 2011 updated equations in power dissipation section ams ag technical content still valid
as1374 datasheet - ordering information www.austriamicrosystems.com/ldos/as1374 revision 1.8 17 - 18 11 ordering information the devices are available as the standard products shown in table 4 . note: all products are rohs compliant and austriamicrosystems green. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect technical support is available at http://www.austriamicrosystems.com/technical-support for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicros ystems.com/distributor table 4. ordering information ordering code marking output voltage 1 output voltage 2 delivery form package as1374-bwlt-285 assh 2.85v 2.85v tape and reel 6-bump wlp AS1374-BWLT1833 assj 1.8v 3.3v tape and reel 6-bump wlp as1374-bwlt1818 assp 1.8v 1.8v tape and reel 6-bump wlp as1374-bwlt1218 assk 1.2v 1.8v tape and reel 6-bump wlp as1374-bwlt1214 assy 1.2v 1.4v tape and reel 6-bump wlp as1374-bwlt18285 assz 1.8v 2.85v tape and reel 6-bump wlp as1374-bwlt1212 assw 1.2v 1.2v tape and reel 6-bump wlp as1374-bwlt1827 astb 1.8v 2.7v tape and reel 6-bump wlp as1374-bwlt1533 1 1. on request astf 1.5v 3.3v tape and reel 6-bump wlp as1374-bwlt1820 1 astg 1.8v 2.0v tape and reel 6-bump wlp as1374-bwlt1821 1 asth 1.8v 2.1v tape and reel 6-bump wlp as1374-bwlt2533 1 asti 2.5v 3.3v tape and reel 6-bump wlp as1374-bwlt 2 2. non-standard devices from 1.2v to 3.6v are available in 50mv steps. for more information and inquiries contact http://www.austriamicrosystems.com/contact ____ tbd tbd tape and reel 6-bump wlp ams ag technical content still valid
as1374 datasheet - ordering information www.austriamicrosystems.com/ldos/as1374 revision 1.8 18 - 18 copyrights copyright ? 1997-2011, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact ams ag technical content still valid

▲Up To Search▲

Price & Availability of AS1374-BWLT1833

	To Download AS1374-BWLT1833 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .